1. Field of the Invention
The present invention relates to a data processor, and more particularly to a data processor which controls execution of instructions by a microprogram.
2. Description of the Prior Art
FIG. 1 is a block diagram of the principal portion of the conventional data processor which controls execution of instructions by a microprogram.
In FIG. 1, reference numeral 1 designates a data bus, which is connected to a memory means, such as a memory (not shown) storing therein the machine language instructions. Numeral 2 designates an instruction register which latches the machine language instructions fetched from the data bus 1 and numeral 3 designates an instruction decoder which decodes the machine language instructions latched in the instruction register 2. As the result of decoding of the machine language instructions, an entry address "a" of the microinstruction is produced and output to a microsequencer 4.
The microsequencer 4 reads microinstructions out of a microinstruction ROM (not shown) in accordance with the entry address output from the instruction decoder 3 and then transmits it to an instruction execution unit 5.
The instruction execution unit 5 executes the microinstruction given from the microsequencer 4.
Operation of the conventional data processor constructed as above-mentioned is as follows:
The machine language instructions are fetched from the data bus 1 to the instruction register 2 to be latched. These instructions are decoded by the instruction decoder 3 so that the entry address "a" of a microinstruction to be executed by the instruction execution unit 5 is produced and given to the microsequencer 4.
The microsequencer 4 reads out the microinstruction from the micro ROM on the basis of the entry address "a". The instruction execution unit 5 executes the instruction read from the micro ROM to execute the machine language instructions.
In addition, the instruction decoder 3 usually comprises a programmable logic array (to be hereinafter called PLA) or the like.
As above-mentioned, the machine language instruction is decoded to produce an entry address of the microinstruction to be executed. However, the entry address of a microinstruction may be required to be changed not only by the kind of instruction but also by the addressing modes of an operand according to the instruction set. Now, as shown in FIG. 2-(a), a case where bit set instructions 6 and 7 are decoded and executed is considered, a processing unit of instruction decoder 3 is assumed to be 16 bits in length. As shown in FIG. 2-(a), it is assumed that the bit set instructions have two addressing designation fields 6b and 7b each containing an operand descriptor. The basic portion of the instruction is described with 32 bits. For simplification of description, the extension portion of the addressing mode is omitted. The bit set instruction, as shown in FIG. 2-(b), specifies the bit position 10 of the processing object by a base address 8 and bit offset 9 therefrom and sets the bit to a logical "1". At first the machine language instruction 6 is decoded by the instruction decoder 3. The operation code 6a is decoded to produce an entry address of a microinstruction corresponding to the machine language instruction 6.
Next, a machine language instruction 7 is decoded by the instruction decoder 3. An operation code 7a is decoded to be discriminated as the bit set instruction, and at this time the addressing mode specified by the operand descriptor 7b shows the base, but the processing when the base is a register is different from the one when the same is a memory. When it is the register, the processing needs only to be executed to the specified bit in the register, but when it is a memory, it is necessary to compute byte address and bit offset of the data to be actually processed from the base address and offset. Accordingly, in this case, it is required to change the entry address of a microinstruction depending not only upon the operation code 7a but also whether the addressing mode specified by the operand descriptor 7b is a register direct mode or others.
Next, as another example, a case where bit field extraction instructions 11, 12 and 13 are executed is considered. In FIG. 3(b) the bit field extraction instruction extracts the bit field 17 shown by a bit width 16 from the bit position represented by the base 14 and offset 15 and writes it in the destination register shown by the field 13b. This instruction, as shown in FIG. 3-(a), has two addressing designation fields 11b, 12b containing the operand descriptors and is assumed to describe the basic portion of instruction by 48 bits. For simplification of explanation, the extension portion of the addressing mode is omitted. The bit field extraction instruction is executed at the point in time when the machine language instruction 13 is decoded. Also in this case the processing to be executed is different depending upon whether the operation object is for the register or the memory. In this case, it is different from the example shown in FIG. 2 in that information is required during the decoding of the machine language instruction 13 which indicates whether the operand specified by the operand descriptor 12b showing the base is register or memory. In this case, usually, it is required to feed back the result of the former instruction decoding to the input of the PLA for instruction decoding, causing the size of the PLA being large.
As above-mentioned, when the processing of an instruction depends on the addressing modes of an operand, the instruction decoder 3 of the conventional data processor is required to detect the instruction, thereby increasing the number of product terms of the PLA constituting the instruction decoder 3, thereby resulting in a large instruction decoder 3. And, in a case where the addressing mode decoding of a just preceding decoding result, such as the aforesaid bit field extraction instruction, is required for the next decoding, the number of input bits of the PLA also increases, and the decoder 3 becomes even larger.
Since the instruction decoder of the conventional data processor is constructed as above-mentioned, when it is required to change the entry address of a microinstruction due to the addressing modes of operand, the number of product terms of the PLA constituting the instruction decoder increases, thereby creating the problem in that the manufacturing cost is high when being a large scale integrated circuit.